This invention generally relates to double-edge triggered flip flops, and more specifically, the invention relates to scannable, double-edge triggered flip-flops.
A flip-flop is an electronic circuit that stores a selected logical state in response to a clock pulse and one or more data input signals. Flip-flops are used in to computational circuits. In these circuits, the flip-flops operate in selected sequences during recurring clock intervals to capture and hold certain data for a period of time sufficient for the other circuits within the system to further process that data. At each clock signal, data are stored in a set of flip-flops whose outputs are available to be applied as inputs to other combinatorial or sequential circuitry during successive clock signals. In this manner, sequential logic circuits are operated to capture, store and transfer data during the successive clock signals.
Most flip-flops are designed to store the logical state represented by an input signal present when a leading edge of a clock pulse is received. Other flip-flops store the logical state indicated by an input signal on receipt of the trailing edge of a clock pulse. Still other flip-flops store data on both the leading edge and the trailing edge of a clock pulse. These latter flip-flops are referred to as double-edge triggered flip flops, or DETFs.
Double edge triggered flip-flops are commonly used in circuits where it is desirable to have a fast clock as well as the normal system clock. As it is also desirable to minimize clock distribution to save layout space, double edge triggered flip-flops offer an option of providing components operating at more than one speed of operation but which require only a single clock. Such techniques also have advantages in saving power, since it is only necessary to generate one source clock signal for two speeds of operation. In particular, since power consumption of the clock distribution network is proportional to the frequency of the clock, achieving a certain speed of operation using a half-speed clock source will reduce by half the power consumption of the clock network, when compared to single edge flip-flop operation.
It is often desirable or necessary to test the functionality of flip-flops, and scan testing is one well known way to do this. In scan testing, known signals are applied to a specific input of the flip flop, and the output of the flip-flop is checked to determine if that output is what the input signals were expected to produce. The input of the flip-flop to which these test signals are applied is referred to as the scan input, and commonly flip-flops have one input that is dedicated primarily or exclusively for this purpose.
Known double-edge flip-flop designs are not scannable. A loss of scan-based test capability is a severe detriment to product quality and/or time-to-market. A loss of clock-gating capability eliminates a means of reducing clock network power based upon transition, or state change, requirements at the flip-flops. The loss of clock-gating capability also eliminates the DETFs power reduction benefits, or even increases power, for those designs whose flip-flops do not require transitions at each clock edge.